Threshold Logic Based Adders Using Floating-Gate Circuits

Rearranging of the logic equations which define the carry lookahead principle and using floating gate circuits allow us to obtain adders with a better performance than the traditional ones. The functions defining functionality of the adder are expressed as threshold functions which have been implemented by resorting to νMOS circuits. A 64 bit adder has been implemented using this approach in a 0.8μm double poly CMOS process. It exhibits a delay under 6 ns which halves the delay of a conventional implementation in the same technology and it consumes less power over 50 MHz. Key-Words: Threshold Logic, Floating-Gate Circuits, Arithmetic Circuits, Carry Lookahead Adders